A NEW STRUCTURE OF FIVE-LEVEL DIODE CLAMPED INVERTER WITH REDUCING ITS ELEMENTS

ABSTRACT At the high power switching circuit's applications, when the harmonic distortion is harmful, a multi-level diode clamped inverter is useful, especially when reduced total harmonic distortion and high power are desired. But when the levels get a rise, number of semiconductors are also rising, which leads to many problems such as increasing cost, losses, installation area, and total harmonic distortion. Many researchers have tried to find solutions to these problems. In this sense, this paper focuses on: a) build a new structure of five level diode clamped inverter. b) Increase the efficiency of the inverter by reducing the number of switches. c) Reduce the total harmonic distortion.


INTRODUCTION
A multi-level invertor was lunched in the seventies of the previous century.Using of multilevel invertor was limited to simple levels.With the developing of time and the increasing applications, the multi-level inverter evolved and the electronic circuits developed to have complex forms and higher levels.
The power electronics have pushed major awareness to multi-level inverters as a novel kind of power converters.Multi-level inverters divided into three topologies, flying capacitors inverter (Kou, 2003), diode clamped inverter (Chen, 2006, Bender, 2006and Cheng 2006), and cascade H bridge inverter (Zhang, 2001, Watson, 2007, Malinowski, 2009).These three types commonly depend on the source of the voltages.There are other types which rely on the adopted source as the source of current (Shen, 2002).
Many research articles have found in the literature about the multi-level diode clamped inverter.
For examples, these research papers published by (Rodriguez et al. 2010, Jayasinghe et al. 2011, Chaturvedi et al. 2011).Fig. 1 shows the three level diode clamped inverter as an example.The main reason for using multi-level inverters is to lower voltage compression on the switches, relegate of electromagnetic interference trouble, and reduce harmonics, and reduce losses (Rodriguez, 2002).The multi-level diode clamped inverter is frequently used in many applications because it provides a high efficiency for switching at the fundamental frequency.
The benefit of using diode because it gives a finite value of voltage leading to reduce compression on the devices.However, there are few disadvantages of using diode clamped inverter.For example, when the levels get rise more than three levels or five levels, it will be difficult due to that it needs more and more elements (diodes, capacitors, and switches), which leads to increase in switching losses and cost.In addition to complexity in switching control and structure (Newton, 1998;Yuan, 1998).Many research have been done to overcome these drawbacks.

MULTI-LEVEL DIODE CLAMPED INVERTER (BACKGROUND)
Normally the main circuit of the n-level diode clamped inverter has [2(n-1)] switches, [(n-1)]   capacitor, and [(n-1) (n-2)] diodes (Yuan, 2000).So, the five-level diode clamped inverter can be configured as shown in the Fig. 2. By using eight switches, four capacitors, and twelve diodes, capacitor voltage balancing, and regulation are investigated (Ishida, 2002;Pan, 2005).Here, the dc voltage source considered as a constant.The voltage in every capacitor is considered the same.Thus, voltage compression on every switch is (Vdc/4).Table 1 lists the modes of switches to the five-level diode clamped inverter with the magnitude of the output voltage.Each mode has four switches (ON) and four switches (OFF).Number one indicates that the switch is ON and zero indicates that switch is OFF.By changing these modes, different output can be achieved.

PROPOSED FIVE LEVEL DIODE CLAMPED INVERTER
A proposed five level diode clamped inverter has six switches, four capacitors, and six diodes as shown in Fig. 3.The proposed inverter gives same levels with less elements.Here, the dc bus voltage divided into five levels by four capacitors connected in series C1 to C4. Center point n can be defined as a neutral point.
Vdc/4 generated when switches 2 and 3 are ON, switches 1,4,5 and 6 are OFF.Zero voltage generated when switches 3 and 4 are ON, switches 1,2,5 and 6 are OFF.-Vdc/2 generated when switches 4 and 5 are ON, switches 1,2,3 and 6 are OFF.-Vdc/4 generated when switches 4,5 and 6 are ON, switches 1,2 and 3 are OFF, as listed in Table 2.The most popular way is pulse width modulation (Yuan, 2000;Chaturvedi et al., 2011;Jayasinghe et al., 2011).Using direct pulse generator in proposed inverter by depending on the next table.

Switch no.
dc/4 V - Providing a square wave at constant intervals in MATLAB program called pulse generator, by using source block parameters for each switch, depending on Table 2, choosing the phase delay, period and pulse width for switch 1, then switch 1 has one time ON at Vdc/2 and OFF for all other times in period, thus it works for 20% (periodicity for each cycle).
Switch 1 works at first column without any delay, therefor phase delay is zero (work directly with first pulse) and so on for all switches as shown in Fig. 5. Putting these parameters for all switches depending on table 2 to get the desirable output voltage.Table 3 shows the comparison between the classical and the proposed topology of five level diode clamped inverter.The proposed inverter gives same levels with less elements and lower THD.

CONCLUSION
A multi-level diode clamped inverter is useful to be used in the high power applications, especially when reducing total harmonic distortion and high power are desired.
When the levels get rise, number of semiconductors are rise also.This drives to many problems such as increasing cost, losses, installation area and total harmonic distortion.
The proposed five-level diode clamped inverter solve all the previous problems.It can produce same number of voltage levels with lower number of elements (switches and diodes) and lower total harmonic distortions compared to the classical inverters.
By using least number of switches and gate trigger circuits, there by guarantee the minimum switching losses, reducing size, installation cost, and maximum efficiency.

Fig. 5 .
Fig. 5. Pulse width and Phase delay for Upper and Lower Switches.This inverter prepared according to the next specifications:-