REDUCING LDPC DECODER COMPLEXITY BY USING FPGA BASED ON MIN SUM ALGORITHM
DOI:
https://doi.org/10.30572/2018/KJE/130105Abstract
Low-Density Parity-Check (LDPC) code approaches Shannon–limit execution for twofold field and long code lengths. The point of this work is to propose an LDPC calculation for Min Sum (MS) deciphering and playing out its equipment execution investigation inside a proposed communication framework. The MS calculation principally utilizes the base and expansion finding procedure. The quantity of increases is subsequently altogether diminished, which tends to decrease the execution intricacy. The consequences of the reenactment show that the proposed MS interpreting calculation performs the same as the translating of the Sum-Product Algorithm (SPA) while keeping up with the principle highlights of the MS disentangling. The further developing execution by diminishing the number of stages in the deciphering system, diminishing the intricacy of the implementation of the Field Programmable Gate Array (FPGA).
Downloads
References
Shannon, Claude Elwood. "A mathematical theory of communication." ACM SIGMOBILE mobile computing and communications review 5.1 (2001): 3-55.
MacKay, David JC, and Radford M. Neal. "Near Shannon limit performance of low-density parity check codes." Electronics letters 32.18 (1996): 1645-1646.
MacKay, David JC. "Good error-correcting codes based on very sparse matrices." IEEE transactions on Information Theory 45.2 (1999): 399-431.
Tomlinson M., Tjhai C.J., Ambroze M.A., Ahmed M., Jibril M. (2017) LDPC Codes. In: Error-Correction Coding and Decoding. Signals and Communication Technology. Springer, Cham. https://doi.org/10.1007/978-3-319-51103-0_12
Kalsi, Arvinder Pal Singh, Rajesh Guide Khanna, and Sanjay Guide Kumar. SMT-8036 based implementation of secured adaptive Software Defined Radio system for LDPC coded modulation techniques. Diss. 2012.
Roh, Si-Dong, Keol Cho, and Ki-Seok Chung. "Implementation of an LDPC decoder on a heterogeneous FPGA-CPU platform using SDSoC." 2016 IEEE Region 10 Conference (TENCON). IEEE, 2016.
Ceroici, Chris, and Vincent C. Gaudet. "FPGA implementation of a clockless stochastic LDPC decoder." 2014 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2014.
Mooij, Joris M., and Hilbert J. Kappen. "Sufficient conditions for convergence of the sum–product algorithm." IEEE Transactions on Information Theory 53.12 (2007): 4422-4437.
Chen, Jun-Chieh, et al. "A novel broadcast scheduling strategy using factor graphs and sum-product algorithm." IEEE Global Telecommunications Conference, 2004. GLOBECOM'04.. Vol. 6. IEEE, 2004.
Angarita, Fabian, et al. "Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor." IEEE Transactions on Circuits and Systems I: Regular Papers 61.7 (2014): 2150-2158.
WIBERG, N. Codes and Decoding on General Graphs. Linkoping, 1996. Dissertation. Linkoping University. Supervisor prof. Ingemar Ingemarsson.
Ahmed A.Emran, and Elsabrouty, Maha. "Simplified variable-scaled min sum LDPC decoder for irregular LDPC codes." 2014 IEEE 11th Consumer Communications and Networking Conference (CCNC). IEEE, 2014.
Hatami, Homayoon, et al. "A threshold-based min-sum algorithm to lower the error floors of quantized LDPC decoders." IEEE Transactions on Communications 68.4 (2020): 2005-2015.
Jianguang Zhao, Zarkeshvari Farhad, and Banihashemi Amir H., "On implementation of min-sum algorithm and its modifications for decoding low-density parity-check (LDPC) codes." IEEE transactions on communications 53.4 (2005): 549-554.
Jun Heo, and Chugg Keith M. "Optimization of scaling soft information in iterative decoding via density evolution methods." IEEE transactions on communications 53.6 (2005): 957-961.
Mosleh, Mahmood Farhan. "Evaluation of low density parity check codes over various channel types." Engineering and Technology Journal 29.5 (2011): 961-971.
Johnson, Sarah J. "Introducing low-density parity-check codes." University of Newcastle, Australia 1 (2006): 2006.
Mosleh, Mahmood F., Fadhil S. Hasan, and Aya H. Abdulhameed. "Enhancement of Differential Chaos Shift Keying Communication System Based on LDPC Codes." (2020).
Richardson, Tom, and Rudiger Urbanke. "The renaissance of Gallager's low-density parity-check codes." IEEE Communications Magazine 41.8 (2003): 126-131.
Andrews, Kenneth S., et al. "The development of turbo and LDPC codes for deep-space applications." Proceedings of the IEEE 95.11 (2007): 2142-2156.
Sulek, Wojciech, Marcin Kucharczyk, and Grzegorz Dziwoki. "GF (q) LDPC decoder design for FPGA implementation." 2013 IEEE 10th Consumer Communications and Networking Conference (CCNC). IEEE, 2013.
Anantharaman, Rajagopal, Karibasappa Kwadiki, and Vasundara Patel Kerehalli Shankar Rao. "Hardware Implementation Analysis of Min-Sum Decoders." Advances in Electrical and Electronic Engineering 17.2 (2019): 179 - 186.
Downloads
Published
How to Cite
Issue
Section
Categories
License
Copyright (c) 2022 MSc. student, Butheena R. Kadhim, Asst. Prof. Fatih Korkmaz
This work is licensed under a Creative Commons Attribution 4.0 International License.
